Analog-to-digital conversion algorithms implemented in silicon (successive approximation registers or SARs, switched-capacitor and switched-current pipelines, folding, flash, etc.) inherently rely on the stability, and low noise, of some internal reference voltage rails against which the input signals must be weighted. In particular, switched-capacitor implementations draw current out of the reference lines to charge/discharge the capacitors employed for processing the signal (in each stage's Multiplicative Digital-to-Analog Converter, or MDAC), usually taxing the reference lines more than in switched-current implementations. Moreover the flash sub-ADC found in the first stage of a switched-capacitor pipeline conversion chain measures the signal against a resistor (or capacitor) ladder, setting the comparator thresholds. Consequently, any error and/or noise affecting the voltage references directly impacts the performance of the whole ADC, without any possibility of correction unless some form of complicated, time-consuming background calibration is employed.
The general approaches addressing the need for stable voltage reference generation for an ADC can be divided into two categories: high-impedance and low-impedance implementations.
High-impedance techniques rely upon the adoption of massive external and internal capacitive decoupling. The capacitors are used as reservoirs to provide the charge necessary to supply the instant current required by the pipeline MDACs. Since the charge variation Δq=C·ΔV, the larger the decoupling capacitor C, the lesser the voltage perturbation affecting the voltage levels. Once the momentary current I=dq/dt has flown from the reservoir capacitors to charge up the signal capacitors in the pipelined quantizer, the reference system has a fair amount of time (almost a whole half-clock period in pipeline schemes, see FIG. 10) to replenish the reservoirs in a slow, controlled fashion. Hence, a high-impedance output, slow-response Operational Transconductance Amplifier (OTA) can accomplish this result and be designed for low-consumption and low-noise at one time. Of course the output voltage of the loop established around the opamp can only be as stable as the reference voltage provided at its inputs, hence a stable input voltage will need to be provided first, for example out of a bandgap circuit.
Low-impedance techniques rely, instead, upon the speed and current-drive capability of a voltage buffer to provide temporarily higher currents, when the signal capacitors are being charged. No internal or external decoupling capacitors are employed on the output voltage lines in this approach, since any additional capacitive load would only slow down the settling transient. The speed of the buffer determines the settling time of the reference system, and sets the current consumption of the voltage reference. Class-A buffer solutions are, in general, more power-hungry as compared to Class-B or Class-AB solutions, where variable amounts of current can be delivered to the load without need for static consumption. The choice in this respect will be dictated by the distortion requirements at the end of the charging cycle.
To linearize the output impedance, while reducing it (by the loop gain) at the same time, and to set the voltage to a precise level, in prior art the buffer is usually closed into a negative feedback loop. This prior art configuration adopting a simple emitter-follower is shown in the schematic of circuit 10 in FIG. 1. The circuit 10 providing the desired reference voltage target to the driver/buffer 22 is ideally unaffected by the “kick-back” current surge that has to be provided to the input thereof, hence it can also be designed for low power and heavily filtered for low noise. This circuit 10 is usually implemented as a closed-loop OTA filtered by a capacitor, making the high-impedance approach a subset of this second solution.